This invention relates to a non-volatile semiconductor device having a ferroelectric layer, more specifically to improvement in partial voltage applied to the ferroelectric layer.
FIG. 9 shows a cross section of an essential part of a conventional ferroelectric memory 50. The ferroelectric memory 50 comprises a semiconductor substrate 51 on which are formed in succession; a gate oxide film 54, a floating gate electrode 55, a ferroelectric layer 56, and a control gate electrode 57.
In the ferroelectric memory 50, not much part of the voltage applied to the control gate 57 for switching polarized state is applied to the ferroelectric layer 56. This is because the dielectric constant ∈ of the ferroelectric is much greater (several hundred times) than that of SiO2 or the like, and the capacitance of the ferroelectric layer 56 is much greater than that of the gate oxide film 54. The partial voltages on capacitors connected in series are inversely proportional to their capacities.
To solve the problem, it is proposed for example in the Transaction of 14th Ferroelectric Application Convention, xe2x80x9cDevelopment of Low Dielectric Constant Ferroelectric Material for MFMISFETxe2x80x9d (14th Ferroelectric Application Convention, issued September 1997, pages 31-32) to reduce the capacitance of the ferroelectric layer by developing a ferroelectric material of a smaller dielectric constant, or to increase the capacitance of the insulation film by reducing the thickness of the gate oxide film. However, there is limitation of development of materials. Reducing thickness of the gate oxide film results in a lower dielectric resistance.
A ferroelectric memory transistor 101 shown in FIG. 10 which is intended to solve the above problems is disclosed in JP-A-9-252099. FIG. 10B shows a section XBxe2x80x94XB in FIG. 10A.
The ferroelectric memory transistor 101 comprises, as shown in FIGS. 10A and 10B, a floating gate electrode 124 in the active 15 region 168, on which is formed an insulation film 130, and on which is a ferroelectric layer 134. A contact hole 132 is formed in the inactive region 130. The floating gate electrode 124 and the ferroelectric layer 134 are in mutual contact in the inactive region 130.
In the ferroelectric memory transistor 101, the partial voltage between the floating gate electrode 124 and the substrate region 112 can be reduced and the partial voltage between the floating gate electrode 124 and a control gate 136 can be increased by only changing the area of the contact hole 132. The capacitor constituted between the control gate 136 and a P well 112 in the ferroelectric memory transistor 101 has a capacitance equivalent to the resultant capacitance shown in FIG. 10C in which capacitors CF and CG are connected in series. The capacitance CF is a resultant capacitance resulting from the parallel connection of the capacitors C1 and C2. The capacitance C1 is a capacitance defined with the insulation film 130 and the ferroelectric layer 134 on the active region 168, while the capacitance C2 is a capacitance defined with the ferroelectric layer 134 on the element separation region 114. Since the ferroelectric layer is much higher in dielectric constant than the insulation film, the capacitance CF may be approximated with the capacitance C2. Therefore, the capacitance CF may be reduced by reducing the capacitance C2. This makes it possible to reduce the partial voltage applied to the capacitor CG and increase the partial voltage applied to the capacitor CF.
However, even if the partial voltage between the floating gate electrode 124 and the substrate region 112 is reduced and the partial voltage between the floating gate electrode 124 and the control gate electrode 136 is increased, then the partial voltage applied to the ferroelectric layer 134 on the active region 168 cannot be increased much. This is because the insulation film 130 is much smaller in dielectric constant than the ferroelectric layer 134 and higher partial voltage is applied to the insulation film 130 than to the ferroelectric layer 134 on the active region 168.
Also it is disclosed in JP-A-9-205181, to reduce opposing area by reducing the upper electrode. However, since this method uses the ion milling process, the surface of the ferroelectric layer is damaged.
The above-described problem of reduced partial voltage associated with the ferroelectric memory constituted with the gate insulation film, floating gate electrode, ferroelectric layer, and control gate electrode also occurs in the ferroelectric memory in which there is no floating gate electrode between the gate insulation film and the ferroelectric layer.
The object of the invention is to provide a ferroelectric semiconductor memory device capable of solving the above-described problems, namely capable of applying higher partial voltage by reducing the substantial area of the ferroelectric layer.
The ferroelectric semiconductor memory device of the invention comprises:
A)
a1) a semiconductor substrate having a substrate region of a first conductive type;
a2) a pair of impurity regions of a second conductive type formed on the surface of the first conductive region;
a3) a first insulation film formed on the substrate region between the pair of impurity regions;
a4) a ferroelectric layer formed on the first insulation film;
a5) an upper electrode formed on the ferroelectric layer; and
B) a substantial capacitance reducing insulation film formed between the first insulation film and the upper electrode and only on part of the substrate region between the pair of impurity regions to reduce substantial capacitance of the ferroelectric layer.
The ferroelectric semiconductor memory device of the invention is characterized by comprising:
A)
a1) a semiconductor substrate having a substrate region of a first conductive type;
a2) a pair of impurity regions of a second conductive type formed on the surface of the first conductive region;
a3) a first insulation film formed on the substrate region between the pair of impurity regions;
a4) a ferroelectric layer formed on the first insulation film;
a5) an upper electrode formed on the ferroelectric layer; and
B) a substantial capacitance reducing insulation film formed between the first insulation film and the upper electrode to reduce substantial capacitance of the ferroelectric layer, and having, on the substrate region between the pair of impurity regions, a portion in which only the ferroelectric layer is present and a portion in which the capacitance reducing insulation film and the ferroelectric layer are present in superimposed state.
The method of manufacturing the ferroelectric memory device of the invention is characterized by comprising the steps of:
A)
a1) providing a semiconductor substrate having a substrate region of a first conductive type;
a2) forming a first insulation film in part of the substrate region and on the substrate region;
a3) forming a ferroelectric layer and an upper electrode on the first insulation film;
a4) forming an impurity region of a second conductive type in the substrate region by implanting the second conductive type of impurity using the upper electrode as a mask; and
B) forming a capacitance reducing insulation film between the first insulation film and the upper electrode to reduce substantial capacitance of the ferroelectric layer, and having, on the substrate region and in the lower region of the upper electrode, a portion in which only the ferroelectric layer is present and a portion in which the capacitance reducing insulation film and the ferroelectric layer are superimposed.
The semiconductor memory using a ferroelectric layer of the invention is the one having a ferroelectric memory FET in which a control gate electrode is provided on a semiconductor layer through at least a first insulation film and a ferroelectric layer, with a second insulation film being inserted in part of the upper or lower side of the ferroelectric layer corresponding to part of the area of the ferroelectric layer.
Those features and other objects, applications, effects, etc. of this invention will be apparent in reference to the embodiments and appended drawings.